As the complexity of integrated circuits increases, numerous approaches have been taken to solve the problem of expediently making electrical connections to and between individual devices. This is an important problem in integrated circuit fabrication because not only do electrical contacts and interconnections require space on the integrated circuit chip, but the complexity of the interconnections frequently requires the metallizations to be on more than one level. The former consideration requires minimization of the size of the metallization, and the latter consideration introduces processing complexity.
In a typical multilevel fabrication sequence, windows or vias are first opened in a dielectric layer to expose selected portions of the underlying substrate and then filled with a metal. Substrate is used to mean underlying material and thus may include the Si wafer, source and drain regions, prior interconnections, etc. Metal runners electrically connecting the filled windows are then formed on the dielectric. This is typically done by blanket depositing a metal and then patterning it. Of course, care must be taken to insure that the runners are properly aligned so that they contact the windows.
Although the processing sequence described is conceptually simple, at least three problems are likely to arise. (1) Metals are highly reflective and the optical printing and etching of features in metals is difficult and becomes even more so at submicron dimensions. (2) After the metal runners have been formed, a dielectric is deposited betwen the runners. This dielectric should be free of voids, but depositing such a layer becomes more difficult as runners are more closely spaced and the space available for the dielectric decreases. (3) Accurate pattern transfer from the mast is most easily obtained with a planar surface. As the topography becomes more complex, dielectric smoothing by means of flow or planarization may be required. However, reflow is not always an acceptable procedure since the temperature required for reflow may impair the integrity of lower metal levels. Planarization schemes make the processing more complex.
Some of these problems can be avoided by a technique such as that discussed by Thomas et al. in IEDM Technical Digest, pp, 811-813, Los Angeles, Calif., 1986. A composite dielectric layer, Si.sub.3 N.sub.4 over SiO.sub.2, is patterned to form trenches into which metal is selectively deposited with the nucleation being initiated by a silicon implant. Thus, the problems of filling the spaces between the runners and of obtaining a planar dielectric surface over complex topography are avoided.
Another approach, which also deposits a metal in a trench in a dielectric is described by Wu in Electrochemical Society Proceedings, 87-4, pp. 239-429, 1987. Exemplary sequences are shown in Wu's FIGS. 1 and 3. The first sequence forms the trenches, blanket deposits a metal, deposits and etches a photoresist thus leaving portions of the original trenches full of resist, etches back the metal to expose the dielectric surface using the resist as an etch mark, and strips the resist leaving recessed metal in the dielectric. The second sequence is conceptually somewhat similar although the unwanted metal is removed by a lift-off step.
Neither approach teaches how to make windows that are self-aligned.